Ashok Mehta is the principal instructor at DefineView who has worked in the semiconductor industry for over 20 years in hardware design and verification engineering/management positions at companies such as INTEL, Digital, AMCC and many startups.
He brings to the class real life experience as an end user of HDL/HVL languages and methodologies that he personally deployed working on many successful silicon tape-outs.
He provides practical in-sight to each feature/operator of the language to show exactly how it will help you solve your problem. He has an enthusiastic style of teaching welcoming any/all questions from the class and strives to provide utmost clarity in the answers.
At INTEL, he worked in the Architectural Verification team of the first Pentium and introduced to the company the concepts of verification environments to stress pipelined behavior, directed and constrained random stimulus generation, among other. He also designed a new Bus Functional Language geared to support Pentium’s pipelined bus architecture, snooping behavior and deployed it successfully to find numerous bugs in the Pentium Bus Unit and First Level Cache.
At AMCC, he managed a team that employed the latest in SystemVerilog methodologies using class libraries, assertions, functional cover points and scoreboards to verify a complex L2 cache subsystem.
Ashok was also a hands-on manager at startup companies Chameleon Systems, empowerTel Networks and Nazomi communications.
Ashok has been a member of technical sub-committees on IEEE Verilog- SDF, and EIA 576. Ashok holds a MSEE from University of Missouri-Rolla.
Ashok brings real life end user perspective to the training class.