CONSULTING SERVICES OFFERED

• System Verilog Assertions - Methodology development and coding

  • Enhance existing Verilog or System Verilog Test bench & Design methodology to include assertions and adopt an Assertion Based Verification (ABV) methdology. From our experience, assertions provide the greatest benefit in reduced development && debug time of device under test resulting in better confidence moving towards logic freeze/tapeout.

  • Static Formal methods using SVA properties and tools such as 0-in to adopt to static functional verification methods that complement your simulation based environment.

• Functional Coverage - Methodology development and coding

  • Functional Coverage is achieved using SVA 'cover' of properties and Functional Coverage language features (covergroups, coverpoints, bins, cross, transition, etc) of SV language.

  • Enhance existing Verilog or System Verilog Test bench & Methodology to add Functional Coverage as a key component to reach an objective measure towards the million dollar question "Can we go for logic freeze?".

  • Adoption of Coverage Driven Methodologies.

• Verification Test Plan Development

  • With detailed study and emphasis on "what exactly needs to be verified" before jumping into creating complex DV test benches, we can help you create test plans that will methodically reach the goal of design/RTL freeze. Test plan would use assertions, functional coverage and coverage driven methodologies seeing that you are targetting the main goal of "finding bugs" and objectively reaching verification closure.

• Verification Project Management

  • I have years of experience in weeding through given design specifications and coming up with realistic project plans. I have taken projects all the way from architectural verification phase through logic freeze with first pass silicon success. I derive detailed schedules to see that projects can be tracked daily/weekly with comprehensive bug tracking system and objective ways to measure functional coverage (SVA temporal domain, SV Functional Coverage, code coverage, etc.).

• Verilog Testbench Development

  • Yep, you can still do a lot with a systematic layered approach using Verilog behavioral language and Verilog-2001 constructs, if your schedule/budget does not allow you to fully deploy OVM/VMM type methodologies.

• Gate Level simulations with pre/post layout SDF back annotations; tester vector generation; silicon bringup; etc. are many other areas in which we can help you.

These are just bus a few ways that we can help you.

Please CONTACT US to discuss specific needs of your project.

1. Our collective experience as end users of HDLs/HVLs  in Design and Verification of complex SoCs and Processors, Cache subsystems puts us in a unique position to offer you services that is relevant to your project.

2. We provide real life solutions in methodologies and code development using Verilog, System Verilog, SVA Assertions and Functional Coverage languages.

3. We work with you to deploy Assertion Based Verification (ABV) and Constrained Random Coverage Driven methodologies

Our founder/principal consultant Ashok's extensive experience with Verilog will assist you in enhancing your existing Verilog testbench with SVA and Functional Coverage to let you start harnessing power of System Verilog as you transition to the emerging OVM/VMM methodologies.

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